Jested Liberec 12th IEEE Symposium on Design and Diagnostics of Electronic Systems
logo ddecs 2009 Liberec
April 15-17, 2009, Liberec, Czech Republic
Keynote Speakers
Social Event
E-mail: ddecs
DDECS 2009 - Program
Day Track 1 Track 2
TUE. 14.4. 16:00 18:00   Accompanying Workshop: Digital Circuit Reliability and Availability Improvement 
      (TU Liberec campus, in Czech language)
18:00 19:00 Registration  
WED. 15.4. 07:00 09:00 Registration  
09:00 09:30 Opening Session  
09:30 10:15 Invited Talk 1  
10:15 11:00 Poster Session I.  
11:00 12:00 Session I. ATPG and Fault Simulation Techniques  
12:00 12:10 Break  
12:10 13:10 Session II. Asynchronous Circuit Design  
13:10 14:30 Lunch  
14:30 15:30 Session III. RF and High Speed Circuit Design  
15:30 15:50 Coffee Break  
15:50 16:50 Session IV. Architecture and Symbolic RTL Synthesis  
16:50 17:00 Break  
17:00 18:00 Session V. Memory Design and Test  
18:00 20:00 Dinner  
THU. 16.4. 09:00 09:45 Invited Talk 2  
09:45 10:30 Poster Session II.  
10:30 11:30 Session VI. Power Supply and Interconnect Related Faults Session VII. Industrial Session
11:30 11:40 Break  
11:40 12:40 Session VIII. Student Session: RF and High Speed Circuits Session IX. Student Session: Miscellaneous
12:40 14:10 Lunch  
14:00 22:00 Social Event  
FRI. 17.4. 09:00 09:45 Invited Talk 3  
09:45 10:30 Poster Session III.  
10:30 11:30 Session X. Analog Design and Sensors  
11:30 11:40 Break  
11:40 12:40 Session XI. Off-Line and On-Line Testing  
12:40 12:50 Break  
12:50 13:10 Closing Session  
13:10 14:30 Lunch  
Accompanying Workshop: Digital Circuit Reliability and Availability Improvement (TU Liberec campus, in Czech language)
Safety and Reliability of Railway Interlocking Devices
Radek Dobias
Realiable design for FPGA by place and route processes
Jiri Kvasnicka
Dependable design based on universal blocks
Jaroslav Borecky, Pavel Kubalik 
Dependable modeling using Petri nets
Martin Kohlik
Synchronization of reconfigurable system in FPGA
Jan Balach
Research at the Dept. of Signal Processing, UTIA AV CR, v.v.i. in the frame of the European projects FP6 Aether a FP7 Apple-CORE. Information about the upcoming conferences FPL2009 and FET09.
Martin Danek 
Comparison of the ASIC and FPGA netlist test pattern quality.
Martin Rozkovec
High Availability Fault Tolerant Architectures Implemented into FPGAs
Martin Straka
The Design of Fault Tolerant Systems into FPGA
Zdenek Kotasek
Invited Talk 1
Chair: Hans Manhaeve, Q-Star Test (BEL) 
Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS
Georges Gielen 
Poster Session I.
An SOC Platform for ADC Test and Measurement
Brendan Mullane, Ciaran Macnamee, Vincent o'Brien, Thomas Fleischmann
A Scheme of Logic Self Repair Including Local Interconnects
Tobias Koal, Daniel Scheit, Heinrich T. Vierhaus
Investigating the Linearity of MOSFET-Only Switched-Capacitor Delta-Sigma Modulators Under Low-Voltage Condition
Farhad Alibeygi Parsan, Ahmad Ayatollahi, Adib Abrishamifar
Comparison of Different Test Strategies on a Mixed-Signal Circuit
Juraj Brenkuš, Viera Stopjaková, Ronny Vanhooren, Anton Chichkov
Case Study: A Class E Power Amplifier for ISO-14443A
Elke De Mulder, Wim Aerts, Bart Preneel, Guy Vandenbosch, Ingrid Verbauwhede
Fast Congestion-Aware Timing-Driven Placement for Island FPGA
Jinpeng Zhao, Qiang Zhou, Yici Cai, Xianlong Hong
Analysis and Optimization of Ring Oscillator Using Sub-Feedback Scheme
Hong-Yi Huang, Fu-Chien Tsai
Improve Clock Gating through Power-Optimal Enable Function Selection
Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou
An Utilisation of Boolean Differential Calculus in Variables Partition Calculation for Decomposition of Logic Functions
Stefan Kołodziński, Edward Hrynkiewicz
Session I. ATPG and Fault Simulation Techniques
chair: Chatterjee A., moderator: Kotásek Z.
A Fast Untestability Proof for SAT-based ATPG
Daniel Tille, Rolf Drechsler
The Impact of EFSM Composition on Functional ATPG
Davide Bresolin, Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Tiziano Villa
An Efficient Fault Simulation Technique for Transition Faults in Non-Scan Sequential Circuits
Alberto Bosio, Paolo Bernardi, Patrick Girard, Serge Pravossoudovich, Matteo Sonza Reorda
Session II. Asynchronous Circuit Design
chair: Garbolino T., moderator: Hrynkiewicz E.
Self-Timed Full Adder Designs Based on Hybrid Input Encoding
Balasubramanian P, Edwards D.A., Brej C.
Optimization Concepts for Self-Healing Asynchronous Circuits
Thomas Panhofer, Werner Friesenbichler, Martin Delvai
Asynchronous Two-Level Logic of Reduced Cost
Igor Lemberski, Petr Fišer
Session III. RF and High Speed Circuit Design
chair: Gielen G., moderator: Stopjaková V.
Low-Voltage Low-Power Double Bulk Mixer for Direct Conversion Receiver in 65nm CMOS
Kurt Schweiger, Heimo Uhrmann, Horst Zimmermann
Low Voltage LNA Implementations in 90 nm CMOS Technology for Multistandard GNSS
Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz
BIST-Assisted Wideband Digital Compensation for MB-UWB Transmitters
Shyam Kumar Devarakond, Shreyas Sen and Abhijit Chatterjee
Session IV. Architecture and Symbolic RTL Synthesis
chair: Daněk M., moderator: Fišer P.
Architecture Model for Approximate Palindrome Detection
Tomas Martinek, Jan Vozenilek, Matej Lexa
Packet Header Analysis and Field Extraction for Multigigabit Networks
Petr Kobiersky, Jan Korenek, Libor Polcak
A Symbolic RTL Synthesis for LUT-based FPGAs.
Stanislaw Deniziak, Mariusz Wisniewski
Session V. Memory Design and Test
chair: Sonsa Reorda M., moderator: Ginez O.
Physical Design Oriented DRAM Neighborhood Pattern Sensitive Fault Testing
Yiorgos Sfikas, Yiorgos Tsiatouhas
Using 3-Valued Memory Representation for State Space Reduction in Embedded Assembly Code Model Checking
Thomas Reinbacher, Martin Horauer, Bastian Schlich
Invited Talk 2
Chair: Ondrej Novak, Technical University of Liberec (CZE)
Cognitive Self-Adaptive Computing and Communication Systems: Test, Control and Adaptation
Abhijit Chatterjee 
Poster Session II.
An On-Line Testing Scheme for Repairing Purposes in Flash Memories
Olivier Ginez, Jean-Michel Portal, Hassen Aziza
Power Devices Current Monitoring Using Horizontal and Vertical Magnetic Force Sensor
Martin Donoval, Martin Daricek, Juraj Marek, Viera Stopjaková
Measurement of Power Supply Noise Tolerance of Self-Timed Processor
Taku Sogabe, Toru Nakura, Makoto Ikeda, Kunihiro Asada
Test Scheme for Switched-Capacitor Circuits by Digital Analyses
Yun-Che Wen
Structural Test of Programmed FPGA Circuits
Martin Rozkovec, Ondrej Novak
Low Voltage Precharge CMOS Logic
Yngvar Berg, Omid Mirmotahari
MDCT / IMDCT Low Power Implementations in 90 nm CMOS Technology for MP3 Audio
Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláž, Witold A. Pleskacz
Effective Mars Rover Platform Design with Hardware / Software Co-Design
Gábor Marosy, Zoltán Kovács, Gyula Horváth
Session VI. Power Supply and Interconnect Related Faults
chair: Anheier W., moderator: Gramatová E.
On the Role of the Power Supply as an Entry for Common Cause Faults - An Experimental Analysis
Peter Tummeltshammer, Andreas Steininger
An Analysis of the Timing Behavior of CMOS Digital Blocks under Simultaneous Switching Noise Conditions
Florence Azais, Yves Bertrand, Michel Renovell
Effective BIST for Crosstalk Faults in Interconnects
Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka
Session VII. Industrial Session
chair: Stamenkovic Z., moderator: Pleštil A.
MTPP - Modular Traffic Processing Platform
Jiri Halak, Sven Ubik
Simulation and Planning Method for On-Chip Power Distribution – An Industry Perspective
Qing K. Zhu, Vincent Bars
Experience in Virtual Testing of RSD Cyclic A/D Converters
Miloslav Kubar, Ondrej Subrt, Pravoslav Martinek, Jiri Jakovenko
A 1GHz-GBW Operational Amplifier for DVB-H Receivers in 65nm CMOS
Heimo Uhrmann, Franz Schlögl, Kurt Schweiger, Horst Zimmermann
Session VIII. Student Session: RF and High Speed Circuits
chair: Bosio A., moderator: Steininger A.
0.5V 160-MHz 260uW All Digital Phase-Locked Loop
Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng
A CMOS Amplitude Detector for RF-BIST and Calibration
Sleiman Bou Sleiman, Mohammed Ismail
A 0.18 µm CMOS UWB LNA with New Feedback Configuration for Optimization Low Noise, High Gain and Small Area
Y. C. Chang, H. L. Kao, C. H. Kao, C. H. Yang, Jeffrey S. Fu, Nemai C. Karmakar, L. C. Chang
Session IX. Student Session: Miscellaneous
chair: Bernardi P., moderator: Steininger A.
Hardware Solution of Chaos Based Image Encryption
Jiri Giesl, Ladislav Behal, Karel Vlcek
Diagnosis of Faulty Units in Regular Graphs under the PMC Model
Miroslav Mánik, Elena Gramatová
All Digital Baseband 50 Mbps Data Recovery Using 5x Oversampling With 0.9 Data Unit Interval Clock Jitter Tolerance
Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada
Invited Talk 3
Chair: Zdenek Pliva, Technical University of Liberec (CZE)
Challenges for test and design for test
Anton Chichkov 
Poster Session III.
Contactless Characterization of MEMS Devices Using Optical Microscopy
András Timár, György Bognár
A Comprehensive Approach for Soft Error Tolerant Four State Logic
Werner Friesenbichler, Thomas Panhofer, Martin Delvai
High-Level Symbolic Simulation for Automatic Model Extraction
Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre
Global Parametric Faults Identification with the Use of Differential Evolution
Piotr Jantos, Damian Grzechca, Jerzy Rutkowski
Forward and Backward Guarding in Early Output Logic
Charlie Brej, Doug Edwards
Logic Synthesis Method for Pattern Matching Circuits Implementation in FPGA with Embedded Memories
Grzegorz Borowik, Tadeusz Luba, Bogdan J. Falkowski
Contention-Avoiding Custom Topology Generation for Network-on-Chip
Stanislaw Deniziak, Robert Tomaszewski
Enhanced LEON3 Core for Superscalar Processing
Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz
Session X. Analog Design and Sensors
chair: Azais F., moderator: Vlcek K.
Ultra Low-Voltage Switched Current Mirror
Yngvar Berg, Omid Mirmotahari
Self-Timed Thermal Sensing and Monitoring of Multicore Systems
Kameswar Rao Vaddina, Ethiopia Nigussie, Pasi Liljeberg, Juha Plosila
A CMOS Bio-Impedance Measure System
Alberto Yufera, Adoracion Rueda
Session XI. Off-Line and On-Line Testing
chair: Vierhaus H.T., moderator: Kubátová H.
An Enhanced FPGA-Based Low-Cost Tester Platform Exploiting Effective Test Data Compression for SoCs
L. Ciganda, F. Abate, P. Bernardi, M. Bruno, M. Sonza Reorda
Comprehensive Bridging Fault Diagnosis Based on the SLAT Paradigm
Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
Round-Level Concurrent Error Detection Applied to Advanced Encryption Standard
Flavius Opritoiu, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan