Abhijit Chatterjee Georgia Institute of Technology 777 Atlantic Drive NW Atlanta, USA
Title:  Cognitive Self-Adaptive Computing and Communication Systems: Test, Control and Adaptation    Abstract:    CMOS technology scaling along with the resulting large variability of circuit performance has made post-silicon circuit and algorithmic level built-in test and adaptation/tuning almost a necessity for deeply scaled technologies. Currently, circuits are designed to tolerate worst-case process corners. In addition, circuits as well as demodulation/signal processing algorithms must be designed for worst case operating conditions (e.g. environmental noise). This forces designers to excessively guard band their circuits while using "aggressive" back-end algorithms to support the end application, resulting in unacceptable power-performance-yield tradeoffs. One way to tackle this problem is to design circuits and relevant signal processing algorithms that are cognitive of their environmental operating conditions and manufacturing process conditions and use this cognition to perform self-adaptation that conserves power while maximizing yield and reliability. Such self-adaptation involves incorporation of built-in test, diagnosis and tuning/adaptation mechanisms into the circuits and systems concerned. A key issue is that of test, diagnosis and tuning of complex circuit and system-level parameters that must be evaluated and traded off against one another during the adaptation process without access to complex external test instrumentation.This talk summarizes recent results obtained in the design of such cognitive computing and communication systems and points to directions for future work in this area.
Bio:   Abhijit CHATTERJEE is a Professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received four Best Paper Awards and three Best Paper Award nominations. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. Chatterjee has published over 300 papers in refereed journals and meetings and has 11 patents. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as Chairman and Chief Scientist from 2000 - 2002. He is currently directing research at Georgia Tech in mixed-signal/RF design and test funded by NSF, SRC, MARCO-DARPA and industry.

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	Anton Chichkov On Semiconductor Corp Oudenaarde, Belgium
Title:  Challenges for test and design for test    Abstract:   If test is mentioned normally there are several remarks that have been repeated for the last 20 years. ICs are too fast, patterns are too big, testing is too slow, the test development too costly. Although, the advance of the technology has improved test in general, these statements seems to prevail and sound still valid. One reason is that on every improvement of test strategies there is also improvement of technology and design strategy that keeps the gap open. On the other hand ATE equipment inevitably is build with one generation older technology that keeps the challenge of speed noise and complexity alive. In this presentation the following few challenges for test will be further discussed. How is evolving the gap between test methods tools and equipment on one side and technology, design methodology and design tools on the other? How is evolving the cost of production test equipment and as consequence the cost of test? Is there change in the cost of test development? What about high quality and reliability application testing? And last but not least what about research in the test domain during economic crisis.
Bio:   Anton CHICHKOV graduated in 1990 in VLSI design at the Technical University of Sofia, Bulgaria. He has worked as ASIC designer in automatic test equipment (ATE) development team. In 1998 he received the Ph.D. in Electronics and Computer Science from the Technical University of Lisbon Thesis was in the field of Hardware Software co-design methods and corresponding development tools. He has worked as test engineering and test methodology manager in Alcatel Microelectronics, AMI Semiconductor and ON Semiconductor. He has earned several publications in high speed ASICs design, ASIC emulation techniques, HW/SW co-design, industrial test methods and test development automation. Holds patent on automatic test program generation methods and tools.

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	Georges Gielen Katholieke Universiteit Leuven Departement Elektrotechniek, ESAT-MICAS Kardinaal Mercierlaan 94 B-3001 Leuven, Belgium
Title:  Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS    Abstract:   With the advanced scaling of CMOS technology in the nanometer range, highly integrated mixed-signal systems can be designed. The use of nanometer CMOS, however, poses many challenges. This keynote presentation gives an overview of problems due to increased variability and reliability. Both have to be addressed by the designer, either at IC design time or through reconfiguration at IC run time. Design tools for the efficient analysis and identification of reliability problems in analog circuits is described. Also, run-time circuit adaptation techniques are presented that allow a circuit to recover from degradation failures.
Bio:   Georges G.E. GIELEN received the MSc and PhD degrees in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 1986 and 1990, respectively. He currently is a Full Professor at the Katholieke Universiteit Leuven. His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation (modeling, simulation and symbolic analysis, analog synthesis, analog layout generation, analog and mixed-signal testing). He has authored five books and more than 300 papers in journals and conference proceedings. He is Fellow of the IEEE and served as the 2005 President of the IEEE Circuits And Systems (CAS) Society.